The present invention relates to one cycle (also known as single cycle) power factor correction (PFC) converters, and in particular, to a simplified circuit for establishing the ramp signal and clock signal in such converter circuits. In particular, the present invention provides a method and circuit for generating a combined ramp and oscillator signal for such converter circuits.
A critical requirement to achieve near unity power factor, when utilizing the single cycle control architecture, is to establish a pulse width modulation (PWM) ramp reference that integrates the error signal over the switching period (T) of the controller. In this architecture, the bandwidth of the error amplifier that establishes the error signal (COMP) is rolled off such that it is much lower than the switching frequency of the controller. Thus, from one cycle to the next there is little or no change in the COMP signal so it can be considered as a nearly DC signal.
FIG. 1 shows the expected ideal behavior of the ramp signal for two different error amplifier COMP signals, VCOMP1 and VCOMP2. FIG. 2 shows a prior art single cycle control power factor correction boost converter circuit. FIG. 3 shows the internal circuitry of the controller 1 of FIG. 2.
The controller 1 of FIG. 2 controls the switch Q1 to achieve power factor correction. Energy is stored in the inductor L when the switch Q1 is turned on and when it is turned off, the charge in the inductor is transferred to the output and stored in the storage capacitor C to power the load.
The controller 1 operates to increase the power factor of the circuit so that the load approximates a purely resistive load as reflected by the current at the AC input being nearly in phase with the AC voltage.
FIG. 3 shows details of the controller 1 of FIG. 2. The feedback voltage is provided at terminal VFB via the voltage divider R1, R2 and R3 provided across the output of the converter. See FIG. 2. The voltage is fed to an error amplifier EA where it is compared to a reference voltage VREF. The reference voltage establishes the desired converter output voltage. The error signal COMP signifies the deviation of the output voltage from the desired output voltage. The error amplifier output is designated as the voltage COMP. The error amplifier output COMP is provided to a GM amplifier 50 that converts the COMP voltage to a current which charges a capacitor C provided at its output. The capacitor C integrates the input of the amplifier 50 producing a ramp signal RAMP. The ramp signal is fed to a PWM comparator 60 where the ramp signal is compared to the adjusted error amplifier's signal COMP which has been adjusted by a summing stage 52 based upon the sensed inductor current at ISNS sensed across a resistor RS by current sense amplifier CSA. See FIG. 2. In the PWM comparator 60, the comparison of the adjusted error amplifier signal 61 with the ramp produces a pulse when the ramp exceeds this adjusted error amplifier signal 61. The pulse at the output of the PWM comparator 60 is fed via gates 62 and 63 to PWM latch 65 where it resets and turns off the gate drive to the switch Q1 via gate 64 and driver 67. The gate drive of the switch Q1 is turned on by a clock signal provided by a clock oscillator 70 at the beginning of the clock cycle. Accordingly, when the clock pulse occurs, the latch 65 sets the gate high turning the switch Q1 on and when the ramp signal exceeds the error signal, the latch is reset and the gate drive is removed. When the latch is reset, a reset signal is provided to discharge the capacitor C via a switch 80, thereby allowing the single cycle control cycle to begin again.
FIG. 3 shows certain additional fault protective functions including an overvoltage protection OVP function which will reset the latch 65 and turn off the gate drive in the event of an overvoltage condition at the output as determined by the resistor divider comprising resistors R4, R5 and R6 (FIG. 2). In addition, a fault protection, open loop protection and output undervoltage circuit is provided that monitors the feedback signal to provide a fault signal in the event of a fault to turn off the gate drive. Further, there is typically provided a UVLO circuit and a maximum duty cycle unit, as shown in FIG. 3.
Turning now to FIG. 1, at the beginning of each clock cycle, the ramp starts from zero volts and then linearly rises over the switching period. To achieve the desired wave shape, the slope of the ramp must be such that the ramp terminates at VCOMP at the end of the cycle. At the end of the cycle, the ramp is reset to zero volts and the cycle starts again. In the drawing, two different ramps for two different COMP voltages are shown. Both start at zero yet terminate at the same time (T) at the appropriate voltage VCOMPX.
The traditional architecture used to implement the one cycle PFC controller involves providing the clock circuit 70 and the ramp circuit as shown in FIG. 3 which closely matches the components of the clock circuit. The requirement for good power factor correction is that at the end of the clock cycle the ramp voltage equals VCOMP. Any error in this voltage results in significant loss of power factor. Unavoidable mismatches between clock and ramp voltage result in significant loss of power factor. Unavoidable mismatches between clock and ramp components as well as offset terms within amplifiers when utilizing this traditional method lead to significant errors in the ramp. Static trimming of the product helps to mitigate these errors at some operating point. However, it cannot provide sufficient mitigation over the full operating range of the circuit, and is useless if the frequency is user-programmable.
In U.S. patent application Ser. No. 11/207,509 referred to above, an active calibration of the ramp is described. This method comes very close to achieving the desired ramp. In this technique, the ramp slope is adjusted cycle to cycle by a circuit that compares a ramp peak to the error signal. If the slope is too flat, the calibrator increases it on the next cycle. If the slope is too steep, then the slope is decreased in the next cycle. Offset errors and propagation delay issues in the calibration circuit can lead to errors in the ramp. However, these errors are small enough so that this technique provides accurate PFC. Drawbacks to this technique are first, dithering in the calibration circuit leads to dithering in the duty cycle that many systems cannot tolerate and secondly, the circuit is more complex so the silicon required to build the ramp and calibrator can be significant.